1. Field of the Invention
The present invention relates to a display device. More particularly, the present invention relates to an array substrate, a manufacturing method of the same and a fabricating method of a display device including the array substrate.
2. Discussion of the Related Art
According to the development of the information, society's needs for various display devices which display images are increasing. In recent years, flat panel display devices such as an liquid crystal display (LCD) device, a plasma display panel (PDP), and an organic light emitting diode (OLED) are adopted. Among these flat panel display devices, the LCD device is widely used since it is compact-sized, light weight, thin, and can be driven with low power.
The pixel areas of this display are defined by crossing gate lines and data lines each other and disposed in matrix structure. In each of the pixel areas, a switching device such as a thin film transistor (TFT) and a pixel electrode connected to the TFT are disposed, and widely adopted is an active matrix type where a data signal applied to the pixel area is controlled by the switching device.
An active matrix display device includes an array substrate having a gate line, a data line, a switching device, and a pixel electrode, which is explained with reference to the attached drawings.
FIG. 1 is a cross-sectional view of an array substrate of an active matrix display device according to the related art.
As shown in FIG. 1, a gate line 22, a gate electrode 24, and a gate pad 26 are formed on a substrate 10. The gate electrode 24 is connected to the gate line 22 and a gate pad 26 is positioned at one end of the gate line 22.
A gate insulation layer 30 is formed on the gate line 22, the gate electrode 24, and a gate pad 26.
An active layer 42 of intrinsic silicon is formed on the gate insulation layer 30 over the gate electrode 24, and an ohmic contact layer 44 made of impurity-doped silicon is formed on the active layer 42.
On the ohmic contact layer 44, a data line 52, a source electrode 54, a drain electrode 56 and a data pad 58 are formed. The source electrode 54 is connected to the data line 52, the drain electrode 56 is spaced apart from the source electrode 54, and the data pad 58 is positioned at one end of the data line 52.
On the data line 52, the source electrode 54, the drain electrode 56, and the data pad 58, a passivation layer 60 is formed. The passivation layer 60 includes a drain contact hole 60a exposing the drain electrode 56, a gate pad contact hole 60b exposing the gate pad 26, and a data pad contact hole 60c exposing the data pad 58. Here, the gate pad contact hole 60b is formed by penetrating the gate insulation layer 30.
On the passivation layer 60, a pixel electrode 72, a gate pad terminal 74, and a data pad terminal 76 are formed. The pixel electrode 72 is connected to the drain electrode 56 through the drain contact hole 60a, the gate pad terminal 74 is connected to the gate pad 26 through the gate pad contact hole 60b, and the data pad terminal 76 is connected to the data pad 58 through the data pad contact hole 60c. 
Recently, since display devices become larger and are required to have a high resolution characteristic, the gate line 22 and the data line 52 become longer. This causes increase of the resistivity of the lines, resulting in delay of signals. Further, since the driving speed becomes higher, load on the lines increases.
To solve these problems, materials of relatively low specific resistance such as copper are adopted for gate and data lines 22 and 52.
Since copper is easily affected by the etching solution, the gate lines 22 and the data lines 52 can be damaged during forming of the contact holes 60a, 60b and 60c. That is to say, the drain contact hole 60a and the data pad contact hole 60c are formed by etching only the passivation layer 60, but the gate pad contact hole 60b is formed by etching both of the passivation layer 60 and the gate insulation layer 30. This means that while forming the gate pad contact hole 60b, the drain electrode 56 and the data pad 58 are exposed earlier and are damaged by the etching solution. This causes increase of contact resistance between the pixel electrode 72 and the drain electrode 56, and between the data pad terminal 76 and the data pad 58.